/*
 * @Author: Laputa
 * @Version: V0.0
 * @Date: 2023-12-20 17:19:40
 * @LastEditors: Laputa
 * @LastEditTime: 2024-01-24 14:09:47
 * @Description: 
 * 
 * Copyright (c) 2023 by Levetop, All Rights Reserved. 
 */

#ifndef _LT168_QSPI_H
#define _LT168_QSPI_H

#include "LT168.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/
/* QSPI CTRLR0 */
#define QSPI_CTRLR0_DFS_MASK                               (0x1FU)
#define QSPI_CTRLR0_DFS_SHIFT                              (0U)
#define QSPI_CTRLR0_DFS(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_DFS_SHIFT)) & QSPI_CTRLR0_DFS_MASK)

#define QSPI_CTRLR0_FRF_MASK                               (0xC0U)
#define QSPI_CTRLR0_FRF_SHIFT                              (6U)
#define QSPI_CTRLR0_FRF(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_FRF_SHIFT)) & QSPI_CTRLR0_FRF_MASK)

#define QSPI_CTRLR0_SCPH_MASK                              (0x100U)
#define QSPI_CTRLR0_SCPH_SHIFT                             (8U)
#define QSPI_CTRLR0_SCPH(x)                                (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_SCPH_SHIFT)) & QSPI_CTRLR0_SCPH_MASK)

#define QSPI_CTRLR0_SCPOL_MASK                             (0x200U)
#define QSPI_CTRLR0_SCPOL_SHIFT                            (9U)
#define QSPI_CTRLR0_SCPOL(x)                               (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_SCPOL_SHIFT)) & QSPI_CTRLR0_SCPOL_MASK)

#define QSPI_CTRLR0_TMOD_MASK                              (0xC00U)
#define QSPI_CTRLR0_TMOD_SHIFT                             (10U)
#define QSPI_CTRLR0_TMOD(x)                                (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_TMOD_SHIFT)) & QSPI_CTRLR0_TMOD_MASK)

#define QSPI_CTRLR0_SLV_OE_MASK                            (0x1000U)
#define QSPI_CTRLR0_SLV_OE_SHIFT                           (12U)
#define QSPI_CTRLR0_SLV_OE(x)                              (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_SLV_OE_SHIFT)) & QSPI_CTRLR0_SLV_OE_MASK)

#define QSPI_CTRLR0_SRL_MASK                               (0x2000U)
#define QSPI_CTRLR0_SRL_SHIFT                              (13U)
#define QSPI_CTRLR0_SRL(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_SRL_SHIFT)) & QSPI_CTRLR0_SRL_MASK)

#define QSPI_CTRLR0_SSTE_MASK                              (0x4000U)
#define QSPI_CTRLR0_SSTE_SHIFT                             (14U)
#define QSPI_CTRLR0_SSTE(x)                                (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_SSTE_SHIFT)) & QSPI_CTRLR0_SSTE_MASK)

#define QSPI_CTRLR0_CFS_MASK                               (0xF0000U)
#define QSPI_CTRLR0_CFS_SHIFT                              (16U)
#define QSPI_CTRLR0_CFS(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_CFS_SHIFT)) & QSPI_CTRLR0_CFS_MASK)

#define QSPI_CTRLR0_SPI_FRF_MASK                           (0xC00000U)
#define QSPI_CTRLR0_SPI_FRF_SHIFT                          (22U)
#define QSPI_CTRLR0_SPI_FRF(x)                             (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR0_SPI_FRF_SHIFT)) & QSPI_CTRLR0_SPI_FRF_MASK)

/* QSPI CTRLR1 */
#define QSPI_CTRLR1_NDF_MASK                               (0xFFFFU)
#define QSPI_CTRLR1_NDF_SHIFT                              (0U)
#define QSPI_CTRLR1_NDF(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_CTRLR1_NDF_SHIFT)) & QSPI_CTRLR1_NDF_MASK) 

/* QSPI SSIENR */
#define QSPI_SSIENR_SSIC_EN_MASK                           (0x1U)
#define QSPI_SSIENR_SSIC_EN_SHIFT                          (0U)
#define QSPI_SSIENR_SSIC_EN(x)                             (((uint32_t)(((uint32_t)(x)) << QSPI_SSIENR_SSIC_EN_SHIFT)) & QSPI_SSIENR_SSIC_EN_MASK) 

/* QSPI MWCR */
#define QSPI_MWCR_MWMOD_MASK                               (0x1U)
#define QSPI_MWCR_MWMOD_SHIFT                              (0U)
#define QSPI_MWCR_MWMOD(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_MWCR_MWMOD_SHIFT)) & QSPI_MWCR_MWMOD_MASK) 

#define QSPI_MWCR_MDD_MASK                                 (0x2U)
#define QSPI_MWCR_MDD_SHIFT                                (1U)
#define QSPI_MWCR_MDD(x)                                   (((uint32_t)(((uint32_t)(x)) << QSPI_MWCR_MDD_SHIFT)) & QSPI_MWCR_MDD_MASK) 

#define QSPI_MWCR_MHS_MASK                                 (0x4U)
#define QSPI_MWCR_MHS_SHIFT                                (2U)
#define QSPI_MWCR_MHS(x)                                   (((uint32_t)(((uint32_t)(x)) << QSPI_MWCR_MHS_SHIFT)) & QSPI_MWCR_MHS_MASK) 

/* QSPI SER */
#define QSPI_SER_SER_MASK                                  (0x1U)
#define QSPI_SER_SER_SHIFT                                 (0U)
#define QSPI_SER_SER(x)                                    (((uint32_t)(((uint32_t)(x)) << QSPI_SER_SER_SHIFT)) & QSPI_SER_SER_MASK) 

/* QSPI BAUDR */
#define QSPI_BAUDR_SCKDV_MASK                              (0xFFFFU)
#define QSPI_BAUDR_SCKDV_SHIFT                             (0U)
#define QSPI_BAUDR_SCKDV(x)                                (((uint32_t)(((uint32_t)(x)) << QSPI_BAUDR_SCKDV_SHIFT)) & QSPI_BAUDR_SCKDV_MASK) 

/* QSPI TXFTLR */
#define QSPI_TXFTLR_TFT_MASK                               (0x1FU)
#define QSPI_TXFTLR_TFT_SHIFT                              (0U)
#define QSPI_TXFTLR_TFT(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_TXFTLR_TFT_SHIFT)) & QSPI_TXFTLR_TFT_MASK) 

#define QSPI_TXFTLR_TXFTHR_MASK                            (0x1F0000U)
#define QSPI_TXFTLR_TXFTHR_SHIFT                           (16U)
#define QSPI_TXFTLR_TXFTHR(x)                              (((uint32_t)(((uint32_t)(x)) << QSPI_TXFTLR_TXFTHR_SHIFT)) & QSPI_TXFTLR_TXFTHR_MASK) 

/* QSPI RXFTLR */
#define QSPI_RXFTLR_RFT_MASK                               (0x1FU)
#define QSPI_RXFTLR_RFT_SHIFT                              (0U)
#define QSPI_RXFTLR_RFT(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_RXFTLR_RFT_SHIFT)) & QSPI_RXFTLR_RFT_MASK) 

/* QSPI TXFLR */
#define QSPI_TXFLR_TXTFL_MASK                              (0x3FU)
#define QSPI_TXFLR_TXTFL_SHIFT                             (0U)

/* QSPI RXFLR */
#define QSPI_RXFLR_RXTFL_MASK                              (0x3FU)
#define QSPI_RXFLR_RXTFL_SHIFT                             (0U)

/* QSPI SR */
#define QSPI_SR_BUSY_MASK                                  (0x1U)
#define QSPI_SR_BUSY_SHIFT                                 (0U)
#define QSPI_SR_BUSY(x)                                    (((uint32_t)(((uint32_t)(x)) << QSPI_SR_BUSY_SHIFT)) & QSPI_SR_BUSY_MASK) 

#define QSPI_SR_TFNF_MASK                                  (0x2U)
#define QSPI_SR_TFNF_SHIFT                                 (1U)
#define QSPI_SR_TFNF(x)                                    (((uint32_t)(((uint32_t)(x)) << QSPI_SR_TFNF_SHIFT)) & QSPI_SR_TFNF_MASK) 

#define QSPI_SR_TFE_MASK                                   (0x4U)
#define QSPI_SR_TFE_SHIFT                                  (2U)
#define QSPI_SR_TFE(x)                                     (((uint32_t)(((uint32_t)(x)) << QSPI_SR_TFE_SHIFT)) & QSPI_SR_TFE_MASK) 

#define QSPI_SR_RFNE_MASK                                  (0x8U)
#define QSPI_SR_RFNE_SHIFT                                 (3U)
#define QSPI_SR_RFNE(x)                                    (((uint32_t)(((uint32_t)(x)) << QSPI_SR_RFNE_SHIFT)) & QSPI_SR_RFNE_MASK) 

#define QSPI_SR_RFF_MASK                                   (0x10U)
#define QSPI_SR_RFF_SHIFT                                  (4U)
#define QSPI_SR_RFF(x)                                     (((uint32_t)(((uint32_t)(x)) << QSPI_SR_RFF_SHIFT)) & QSPI_SR_RFF_MASK)

#define QSPI_SR_TXE_MASK                                   (0x20U)
#define QSPI_SR_TXE_SHIFT                                  (5U)
#define QSPI_SR_TXE(x)                                     (((uint32_t)(((uint32_t)(x)) << QSPI_SR_TXE_SHIFT)) & QSPI_SR_TXE_MASK) 

#define QSPI_SR_TXE_MASK                                   (0x20U)
#define QSPI_SR_TXE_SHIFT                                  (5U)
#define QSPI_SR_TXE(x)                                     (((uint32_t)(((uint32_t)(x)) << QSPI_SR_TXE_SHIFT)) & QSPI_SR_TXE_MASK) 

/* QSPI IMR */
#define QSPI_IMR_TXEIM_MASK                                (0x1U)
#define QSPI_IMR_TXEIM_SHIFT                               (0U)
#define QSPI_IMR_TXEIM(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_TXEIM_SHIFT)) & QSPI_IMR_TXEIM_MASK) 

#define QSPI_IMR_TXOIM_MASK                                (0x2U)
#define QSPI_IMR_TXOIM_SHIFT                               (1U)
#define QSPI_IMR_TXOIM(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_TXOIM_SHIFT)) & QSPI_IMR_TXOIM_MASK) 

#define QSPI_IMR_RXUIM_MASK                                (0x4U)
#define QSPI_IMR_RXUIM_SHIFT                               (2U)
#define QSPI_IMR_RXUIM(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_RXUIM_SHIFT)) & QSPI_IMR_RXUIM_MASK) 

#define QSPI_IMR_RXOIM_MASK                                (0x8U)
#define QSPI_IMR_RXOIM_SHIFT                               (3U)
#define QSPI_IMR_RXOIM(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_RXOIM_SHIFT)) & QSPI_IMR_RXOIM_MASK) 

#define QSPI_IMR_RXFIM_MASK                                (0x10U)
#define QSPI_IMR_RXFIM_SHIFT                               (4U)
#define QSPI_IMR_RXFIM(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_RXFIM_SHIFT)) & QSPI_IMR_RXFIM_MASK) 

#define QSPI_IMR_XRXOIM_MASK                               (0x40U)
#define QSPI_IMR_XRXOIM_SHIFT                              (6U)
#define QSPI_IMR_XRXOIM(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_XRXOIM_SHIFT)) & QSPI_IMR_XRXOIM_MASK) 

/* QSPI ISR */
#define QSPI_ISR_TXEIS_MASK                                (0x1U)
#define QSPI_ISR_TXEIS_SHIFT                               (0U)
#define QSPI_ISR_TXEIS(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_TXEIS_SHIFT)) & QSPI_ISR_TXEIS_MASK) 

#define QSPI_ISR_TXOIS_MASK                                (0x2U)
#define QSPI_ISR_TXOIS_SHIFT                               (1U)
#define QSPI_ISR_TXOIS(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_TXOIS_SHIFT)) & QSPI_ISR_TXOIS_MASK) 

#define QSPI_ISR_RXUIS_MASK                                (0x4U)
#define QSPI_ISR_RXUIS_SHIFT                               (2U)
#define QSPI_ISR_RXUIS(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_RXUIS_SHIFT)) & QSPI_ISR_RXUIS_MASK) 

#define QSPI_ISR_RXOIS_MASK                                (0x8U)
#define QSPI_ISR_RXOIS_SHIFT                               (3U)
#define QSPI_ISR_RXOIS(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_RXOIS_SHIFT)) & QSPI_ISR_RXOIS_MASK) 

#define QSPI_ISR_RXFIS_MASK                                (0x10U)
#define QSPI_ISR_RXFIS_SHIFT                               (4U)
#define QSPI_ISR_RXFIS(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_RXFIS_SHIFT)) & QSPI_ISR_RXFIS_MASK) 

#define QSPI_ISR_XRXOIS_MASK                               (0x40U)
#define QSPI_ISR_XRXOIS_SHIFT                              (6U)
#define QSPI_ISR_XRXOIS(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_XRXOIS_SHIFT)) & QSPI_ISR_XRXOIS_MASK) 

/* QSPI RISR */
#define QSPI_RISR_TXEIS_MASK                               (0x1U)
#define QSPI_RISR_TXEIS_SHIFT                              (0U)
#define QSPI_RISR_TXEIS(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_RISR_TXEIS_SHIFT)) & QSPI_RISR_TXEIS_MASK) 

#define QSPI_RISR_TXOIS_MASK                               (0x2U)
#define QSPI_RISR_TXOIS_SHIFT                              (1U)
#define QSPI_RISR_TXOIS(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_RISR_TXOIS_SHIFT)) & QSPI_RISR_TXOIS_MASK) 

#define QSPI_RISR_RXUIS_MASK                               (0x4U)
#define QSPI_RISR_RXUIS_SHIFT                              (2U)
#define QSPI_RISR_RXUIS(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_RISR_RXUIS_SHIFT)) & QSPI_RISR_RXUIS_MASK) 

#define QSPI_RISR_RXOIS_MASK                               (0x8U)
#define QSPI_RISR_RXOIS_SHIFT                              (3U)
#define QSPI_RISR_RXOIS(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_RISR_RXOIS_SHIFT)) & QSPI_RISR_RXOIS_MASK) 

#define QSPI_RISR_RXFIS_MASK                               (0x10U)
#define QSPI_RISR_RXFIS_SHIFT                              (4U)
#define QSPI_RISR_RXFIS(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_RISR_RXFIS_SHIFT)) & QSPI_RISR_RXFIS_MASK) 

#define QSPI_RISR_XRXOIS_MASK                              (0x40U)
#define QSPI_RISR_XRXOIS_SHIFT                             (6U)
#define QSPI_RISR_XRXOIS(x)                                (((uint32_t)(((uint32_t)(x)) << QSPI_RISR_XRXOIS_SHIFT)) & QSPI_RISR_XRXOIS_MASK) 

/* QSPI TXOICR */
#define QSPI_TXOICR_TXOICR_MASK                            (0x1U)
#define QSPI_TXOICR_TXOICR_SHIFT                           (0U)
#define QSPI_TXOICR_TXOICR(x)                              (((uint32_t)(((uint32_t)(x)) << QSPI_TXOICR_TXOICR_SHIFT)) & QSPI_TXOICR_TXOICR_MASK) 

/* QSPI RXOICR */
#define QSPI_RXOICR_RXOICR_MASK                            (0x1U)
#define QSPI_RXOICR_RXOICR_SHIFT                           (0U)
#define QSPI_RXOICR_RXOICR(x)                              (((uint32_t)(((uint32_t)(x)) << QSPI_RXOICR_RXOICR_SHIFT)) & QSPI_RXOICR_RXOICR_MASK) 

/* QSPI RXUICR */
#define QSPI_RXUICR_RXUICR_MASK                            (0x1U)
#define QSPI_RXUICR_RXUICR_SHIFT                           (0U)
#define QSPI_RXUICR_RXUICR(x)                              (((uint32_t)(((uint32_t)(x)) << QSPI_RXUICR_RXUICR_SHIFT)) & QSPI_RXUICR_RXUICR_MASK) 

/* QSPI ICR */
#define QSPI_ICR_ICR_MASK                                  (0x1U)
#define QSPI_ICR_ICR_SHIFT                                 (0U)
#define QSPI_ICR_ICR(x)                                    (((uint32_t)(((uint32_t)(x)) << QSPI_ICR_ICR_SHIFT)) & QSPI_ICR_ICR_MASK) 

/* QSPI DMACR */
#define QSPI_DMACR_RDMAE_MASK                              (0x1U)
#define QSPI_DMACR_RDMAE_SHIFT                             (0U)
#define QSPI_DMACR_RDMAE(x)                                (((uint32_t)(((uint32_t)(x)) << QSPI_DMACR_RDMAE_SHIFT)) & QSPI_DMACR_RDMAE_MASK) 

#define QSPI_DMACR_TDMAE_MASK                              (0x2U)
#define QSPI_DMACR_TDMAE_SHIFT                             (1U)
#define QSPI_DMACR_TDMAE(x)                                (((uint32_t)(((uint32_t)(x)) << QSPI_DMACR_TDMAE_SHIFT)) & QSPI_DMACR_TDMAE_MASK) 

/* QSPI DMATDLR */
#define QSPI_DMATDLR_DMATDL_MASK                           (0x1FU)
#define QSPI_DMATDLR_DMATDL_SHIFT                          (0U)
#define QSPI_DMATDLR_DMATDL(x)                             (((uint32_t)(((uint32_t)(x)) << QSPI_DMATDLR_DMATDL_SHIFT)) & QSPI_DMATDLR_DMATDL_MASK) 

/* QSPI DMARDLR */
#define QSPI_DMARDLR_DMARDL_MASK                           (0x1FU)
#define QSPI_DMARDLR_DMARDL_SHIFT                          (0U)
#define QSPI_DMARDLR_DMARDL(x)                             (((uint32_t)(((uint32_t)(x)) << QSPI_DMARDLR_DMARDL_SHIFT)) & QSPI_DMARDLR_DMARDL_MASK) 

/* QSPI IDR */
#define QSPI_IDR_IDCODE_MASK                               (0xFFFFFFFFU)
#define QSPI_IDR_IDCODE_SHIFT                              (0U)
#define QSPI_IDR_IDCODE(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_IDR_IDCODE_SHIFT)) & QSPI_IDR_IDCODE_MASK) 

/* QSPI VIDR */
#define QSPI_VIDR_SSIC_COMP_VERSION_MASK                   (0xFFFFFFFFU)
#define QSPI_VIDR_SSIC_COMP_VERSION_SHIFT                  (0U)
#define QSPI_VIDR_SSIC_COMP_VERSION(x)                     (((uint32_t)(((uint32_t)(x)) << QSPI_VIDR_SSIC_COMP_VERSION_SHIFT)) & QSPI_VIDR_SSIC_COMP_VERSION_MASK) 

/* QSPI DR */
#define QSPI_DR_MASK                                       (0xFFFFFFFFU)
#define QSPI_DR_SHIFT                                      (0U)
#define QSPI_DR(x)                                         (((uint32_t)(((uint32_t)(x)) << QSPI_DR_SHIFT)) & QSPI_DR_MASK) 

/* QSPI RXSDR */
#define QSPI_RXSDR_RSD_MASK                                (0xFFU)
#define QSPI_RXSDR_RSD_SHIFT                               (0U)
#define QSPI_RXSDR_RSD(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_RXSDR_RSD_SHIFT)) & QSPI_RXSDR_RSD_MASK) 

#define QSPI_RXSDR_SE_MASK                                 (0x10000U)
#define QSPI_RXSDR_SE_SHIFT                                (16U)
#define QSPI_RXSDR_SE(x)                                   (((uint32_t)(((uint32_t)(x)) << QSPI_RXSDR_SE_SHIFT)) & QSPI_RXSDR_SE_MASK) 

/* QSPI SPICTRLR0 */
#define QSPI_SPICTRLR0_TRANS_TYPE_MASK                     (0x3U)
#define QSPI_SPICTRLR0_TRANS_TYPE_SHIFT                    (0U)
#define QSPI_SPICTRLR0_TRANS_TYPE(x)                       (((uint32_t)(((uint32_t)(x)) << QSPI_SPICTRLR0_TRANS_TYPE_SHIFT)) & QSPI_SPICTRLR0_TRANS_TYPE_MASK) 

#define QSPI_SPICTRLR0_ADDR_L_MASK                         (0x3CU)
#define QSPI_SPICTRLR0_ADDR_L_SHIFT                        (2U)
#define QSPI_SPICTRLR0_ADDR_L(x)                           (((uint32_t)(((uint32_t)(x)) << QSPI_SPICTRLR0_ADDR_L_SHIFT)) & QSPI_SPICTRLR0_ADDR_L_MASK)

#define QSPI_SPICTRLR0_INST_L_MASK                         (0x300U)
#define QSPI_SPICTRLR0_INST_L_SHIFT                        (8U)
#define QSPI_SPICTRLR0_INST_L(x)                           (((uint32_t)(((uint32_t)(x)) << QSPI_SPICTRLR0_INST_L_SHIFT)) & QSPI_SPICTRLR0_INST_L_MASK)

#define QSPI_SPICTRLR0_WAIT_CYCLES_MASK                    (0xF800U)
#define QSPI_SPICTRLR0_WAIT_CYCLES_SHIFT                   (11U)
#define QSPI_SPICTRLR0_WAIT_CYCLES(x)                      (((uint32_t)(((uint32_t)(x)) << QSPI_SPICTRLR0_WAIT_CYCLES_SHIFT)) & QSPI_SPICTRLR0_WAIT_CYCLES_MASK)

#define QSPI_SPICTRLR0_CLK_STRETCH_EN_MASK                 (0x40000000U)
#define QSPI_SPICTRLR0_CLK_STRETCH_EN_SHIFT                (30U)
#define QSPI_SPICTRLR0_CLK_STRETCH_EN(x)                   (((uint32_t)(((uint32_t)(x)) << QSPI_SPICTRLR0_CLK_STRETCH_EN_SHIFT)) & QSPI_SPICTRLR0_CLK_STRETCH_EN_MASK)

/* QSPI XIPMBR */
#define QSPI_XIPMBR_XIP_MD_BITS_MASK                       (0xFFFFU)
#define QSPI_XIPMBR_XIP_MD_BITS_SHIFT                      (0U)
#define QSPI_XIPMBR_XIP_MD_BITS(x)                         (((uint32_t)(((uint32_t)(x)) << QSPI_XIPMBR_XIP_MD_BITS_SHIFT)) & QSPI_XIPMBR_XIP_MD_BITS_MASK)

/* QSPI XIPIIR */
#define QSPI_XIPIIR_INCR_INST_MASK                         (0xFFFFU)
#define QSPI_XIPIIR_INCR_INST_SHIFT                        (0U)
#define QSPI_XIPIIR_INCR_INST(x)                           (((uint32_t)(((uint32_t)(x)) << QSPI_XIPIIR_INCR_INST_SHIFT)) & QSPI_XIPIIR_INCR_INST_MASK)

/* QSPI XIPWIR */
#define QSPI_XIPWIR_WRAP_INST_MASK                         (0xFFFFU)
#define QSPI_XIPWIR_WRAP_INST_SHIFT                        (0U)
#define QSPI_XIPWIR_WRAP_INST(x)                           (((uint32_t)(((uint32_t)(x)) << QSPI_XIPWIR_WRAP_INST_SHIFT)) & QSPI_XIPWIR_WRAP_INST_MASK)

/* QSPI XIPCR */
#define QSPI_XIPCR_FRF_MASK                                (0x3U)
#define QSPI_XIPCR_FRF_SHIFT                               (0U)
#define QSPI_XIPCR_FRF(x)                                  (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_FRF_SHIFT)) & QSPI_XIPCR_FRF_MASK)

#define QSPI_XIPCR_TRANS_TYPE_MASK                         (0xCU)
#define QSPI_XIPCR_TRANS_TYPE_SHIFT                        (2U)
#define QSPI_XIPCR_TRANS_TYPE(x)                           (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_TRANS_TYPE_SHIFT)) & QSPI_XIPCR_TRANS_TYPE_MASK)

#define QSPI_XIPCR_ADDR_L_MASK                             (0xF0U)
#define QSPI_XIPCR_ADDR_L_SHIFT                            (4U)
#define QSPI_XIPCR_ADDR_L(x)                               (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_ADDR_L_SHIFT)) & QSPI_XIPCR_ADDR_L_MASK)

#define QSPI_XIPCR_INST_L_MASK                             (0x600U)
#define QSPI_XIPCR_INST_L_SHIFT                            (9U)
#define QSPI_XIPCR_INST_L(x)                               (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_INST_L_SHIFT)) & QSPI_XIPCR_INST_L_MASK)

#define QSPI_XIPCR_MD_BITS_EN_MASK                         (0x1000U)
#define QSPI_XIPCR_MD_BITS_EN_SHIFT                        (12U)
#define QSPI_XIPCR_MD_BITS_EN(x)                           (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_MD_BITS_EN_SHIFT)) & QSPI_XIPCR_MD_BITS_EN_MASK)

#define QSPI_XIPCR_WAIT_CYCLES_MASK                        (0x3E000U)
#define QSPI_XIPCR_WAIT_CYCLES_SHIFT                       (13U)
#define QSPI_XIPCR_WAIT_CYCLES(x)                          (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_WAIT_CYCLES_SHIFT)) & QSPI_XIPCR_WAIT_CYCLES_MASK)

#define QSPI_XIPCR_INST_EN_MASK                            (0x400000U)
#define QSPI_XIPCR_INST_EN_SHIFT                           (22U)
#define QSPI_XIPCR_INST_EN(x)                              (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_INST_EN_SHIFT)) & QSPI_XIPCR_INST_EN_MASK)

#define QSPI_XIPCR_CONT_XFER_EN_MASK                       (0x800000U)
#define QSPI_XIPCR_CONT_XFER_EN_SHIFT                      (23U)
#define QSPI_XIPCR_CONT_XFER_EN(x)                         (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_CONT_XFER_EN_SHIFT)) & QSPI_XIPCR_CONT_XFER_EN_MASK)

#define QSPI_XIPCR_XIP_MBL_MASK                            (0xC000000U)
#define QSPI_XIPCR_XIP_MBL_SHIFT                           (26U)
#define QSPI_XIPCR_XIP_MBL(x)                              (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_XIP_MBL_SHIFT)) & QSPI_XIPCR_XIP_MBL_MASK)

#define QSPI_XIPCR_XIP_PREFETCH_EN_MASK                    (0x20000000U)
#define QSPI_XIPCR_XIP_PREFETCH_EN_SHIFT                   (29U)
#define QSPI_XIPCR_XIP_PREFETCH_EN(x)                      (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCR_XIP_PREFETCH_EN_SHIFT)) & QSPI_XIPCR_XIP_PREFETCH_EN_MASK)

/* QSPI XIPSER */
#define QSPI_XIPSER_SER_MASK                               (0x1U)
#define QSPI_XIPSER_SER_SHIFT                              (0U)
#define QSPI_XIPSER_SER(x)                                 (((uint32_t)(((uint32_t)(x)) << QSPI_XIPSER_SER_SHIFT)) & QSPI_XIPSER_SER_MASK)

/* QSPI XRXIOCR */
#define QSPI_XRXIOCR_XRXOICR_MASK                          (0x1U)
#define QSPI_XRXIOCR_XRXOICR_SHIFT                         (0U)
#define QSPI_XRXIOCR_XRXOICR(x)                            (((uint32_t)(((uint32_t)(x)) << QSPI_XRXIOCR_XRXOICR_SHIFT)) & QSPI_XRXIOCR_XRXOICR_MASK)

/* QSPI XIPCTTOR */
#define QSPI_XIPCTTOR_XTOC_MASK                            (0xFFU)
#define QSPI_XIPCTTOR_XTOC_SHIFT                           (0U)
#define QSPI_XIPCTTOR_XTOC(x)                              (((uint32_t)(((uint32_t)(x)) << QSPI_XIPCTTOR_XTOC_SHIFT)) & QSPI_XIPCTTOR_XTOC_MASK)

#define QSPI_STATUS_BUSY                                   (1U)
#define QSPI_STATUS_IDLE                                   (0U)

#define QSPI_STATUS_TxFIFO_NOT_FULL                        (1U)
#define QSPI_STATUS_TxFIFO_FULL                            (0U)

#define QSPI_STATUS_TxFIFO_EMPTY                           (1U)
#define QSPI_STATUS_TxFIFO_NOT_EMPTY                       (0U)

#define QSPI_STATUS_RxFIFO_NOT_EMPTY                       (1U)
#define QSPI_STATUS_RxFIFO_EMPTY                           (0U)

#define QSPI_STATUS_RxFIFO_FULL                            (1U)
#define QSPI_STATUS_RxFIFO_NOT_FULL                        (0U)

#define QSPI_STATUS_ERROR                                  (1U)
#define QSPI_STATUS_NO_ERROR                               (0U)

/**
 * @brief: QSPI Data Frame Size Enumeration
 */
typedef enum qspi_data_frame_size_te{
    QSPI_Data_Frame_Size_4bits  = 3U,  /*!< 4-bits serial data transfer */
    QSPI_Data_Frame_Size_5bits  = 4U,  /*!< 5-bits serial data transfer */
    QSPI_Data_Frame_Size_6bits  = 5U,  /*!< 6-bits serial data transfer */
    QSPI_Data_Frame_Size_7bits  = 6U,  /*!< 7-bits serial data transfer */
    QSPI_Data_Frame_Size_8bits  = 7U,  /*!< 8-bits serial data transfer */
    QSPI_Data_Frame_Size_9bits  = 8U,  /*!< 9-bits serial data transfer */
    QSPI_Data_Frame_Size_10bits = 9U,  /*!< 10-bits serial data transfer */
    QSPI_Data_Frame_Size_11bits = 10U, /*!< 11-bits serial data transfer */
    QSPI_Data_Frame_Size_12bits = 11U, /*!< 12-bits serial data transfer */
    QSPI_Data_Frame_Size_13bits = 12U, /*!< 13-bits serial data transfer */
    QSPI_Data_Frame_Size_14bits = 13U, /*!< 14-bits serial data transfer */
    QSPI_Data_Frame_Size_15bits = 14U, /*!< 15-bits serial data transfer */
    QSPI_Data_Frame_Size_16bits = 15U, /*!< 16-bits serial data transfer */
    QSPI_Data_Frame_Size_17bits = 16U, /*!< 17-bits serial data transfer */
    QSPI_Data_Frame_Size_18bits = 17U, /*!< 18-bits serial data transfer */
    QSPI_Data_Frame_Size_19bits = 18U, /*!< 19-bits serial data transfer */
    QSPI_Data_Frame_Size_20bits = 19U, /*!< 20-bits serial data transfer */
    QSPI_Data_Frame_Size_21bits = 20U, /*!< 21-bits serial data transfer */
    QSPI_Data_Frame_Size_22bits = 21U, /*!< 22-bits serial data transfer */
    QSPI_Data_Frame_Size_23bits = 22U, /*!< 23-bits serial data transfer */
    QSPI_Data_Frame_Size_24bits = 23U, /*!< 24-bits serial data transfer */
    QSPI_Data_Frame_Size_25bits = 24U, /*!< 25-bits serial data transfer */
    QSPI_Data_Frame_Size_26bits = 25U, /*!< 26-bits serial data transfer */
    QSPI_Data_Frame_Size_27bits = 26U, /*!< 27-bits serial data transfer */
    QSPI_Data_Frame_Size_28bits = 27U, /*!< 28-bits serial data transfer */
    QSPI_Data_Frame_Size_29bits = 28U, /*!< 29-bits serial data transfer */
    QSPI_Data_Frame_Size_30bits = 29U, /*!< 30-bits serial data transfer */
    QSPI_Data_Frame_Size_31bits = 30U, /*!< 31-bits serial data transfer */
    QSPI_Data_Frame_Size_32bits = 31U  /*!< 32-bits serial data transfer */
} qspi_data_frame_size_te;

/**
 * @brief: QSPI Data Frame Format Enumeration
 */
typedef enum qspi_data_frame_format_te{
    QSPI_Data_Frame_Format_Motorola          = 0U, /*!< Motorola SPI Frame Format  */
    QSPI_Data_Frame_Format_Texas_Instruments = 1U, /*!< Texas Instruments SSP Frame Format  */
    QSPI_Data_Frame_Format_Microwire         = 2U  /*!< National Semiconductors Microwire Frame Format  */
} qspi_data_frame_format_te;

/**
 * @brief: QSPI Serial Clock Phase Enumeration
 */
typedef enum qspi_serial_clock_phase_te{
    QSPI_Serial_Clock_Toggles_Middle_Bit = 0U, /*!< Serial clock toggles in middle of first bit  */
    QSPI_Serial_Clock_Toggles_Start_Bit  = 1U, /*!< Serial clock toggles at start of first bit  */
} qspi_serial_clock_phase_te;

/**
 * @brief: QSPI Serial Clock Polarity Enumeration
 */
typedef enum qspi_serial_clock_polarity_te{
    QSPI_Serial_Clock_Polarity_Inactive_Low  = 0U, /*!< Inactive state of serial clock is low */
    QSPI_Serial_Clock_Polarity_Inactive_High = 1U, /*!< Inactive state of serial clock is high  */
} qspi_serial_clock_polarity_te;

/**
 * @brief: QSPI Transfer Mode Enumeration
 */
typedef enum qspi_transfer_mode_te{
    QSPI_Mode_Tx_and_Rx   = 0U, /*!< Transmit & Receive; Not Applicable in enhanced SPI operating mode */
    QSPI_Mode_Tx_Only     = 1U, /*!< Transmit only mode; Or Write in enhanced SPI operating mode */
    QSPI_Mode_Rx_Only     = 2U, /*!< Receive only mode; Or Read in enhanced SPI operating mode */
    QSPI_Mode_Eeprom_Read = 3U, /*!< EEPROM Read mode; Not Applicable in enhanced SPI operating mode */
} qspi_transfer_mode_te;

/**
 * @brief: QSPI Control Frame Size Enumeration
 */
typedef enum qspi_control_frame_size_te{
    QSPI_Control_Frame_Size_1bits  = 0U,  /*!< 1-bit Control Word */
    QSPI_Control_Frame_Size_2bits  = 1U,  /*!< 2-bit Control Word */
    QSPI_Control_Frame_Size_3bits  = 2U,  /*!< 3-bit Control Word */
    QSPI_Control_Frame_Size_4bits  = 3U,  /*!< 4-bit Control Word */
    QSPI_Control_Frame_Size_5bits  = 4U,  /*!< 5-bit Control Word */
    QSPI_Control_Frame_Size_6bits  = 5U,  /*!< 6-bit Control Word */
    QSPI_Control_Frame_Size_7bits  = 6U,  /*!< 7-bit Control Word */
    QSPI_Control_Frame_Size_8bits  = 7U,  /*!< 8-bit Control Word */
    QSPI_Control_Frame_Size_9bits  = 8U,  /*!< 9-bit Control Word */
    QSPI_Control_Frame_Size_10bits = 9U,  /*!< 10-bit Control Word */
    QSPI_Control_Frame_Size_11bits = 10U, /*!< 11-bit Control Word */
    QSPI_Control_Frame_Size_12bits = 11U, /*!< 12-bit Control Word */
    QSPI_Control_Frame_Size_13bits = 12U, /*!< 13-bit Control Word */
    QSPI_Control_Frame_Size_14bits = 13U, /*!< 14-bit Control Word */
    QSPI_Control_Frame_Size_15bits = 14U, /*!< 15-bit Control Word */
    QSPI_Control_Frame_Size_16bits = 15U, /*!< 16-bit Control Word */
} qspi_control_frame_size_te;

/**
 * @brief: QSPI Frame Format Enumeration
 */
typedef enum qspi_frame_format_te{
    QSPI_Frame_Format_Standard_SPI = 0U, /*!< Standard SPI Format */
    QSPI_Frame_Format_Dual_SPI     = 1U, /*!< Dual SPI Format */
    QSPI_Frame_Format_Quad_SPI     = 2U, /*!< Quad SPI Format */
    QSPI_Frame_Format_Octal_SPI    = 3U, /*!< Octal SPI Format */
} qspi_frame_format_te;

/**
 * @brief: QSPI Status Type Enumeration
 */
typedef enum qspi_status_type_te{
    QSPI_Status_BUSY = 0U, /*!< QSPI Busy */
    QSPI_Status_TFNF = 1U, /*!< QSPI Transmit FIFO Not Full */
    QSPI_Status_TFE  = 2U, /*!< QSPI Transmit FIFO Empty */
    QSPI_Status_RFNE = 3U, /*!< QSPI Receive FIFO Not Empty */
    QSPI_Status_RFF  = 4U, /*!< QSPI Receive FIFO Full */
    QSPI_Status_TXE  = 5U, /*!< QSPI Transmission Error */
} qspi_status_type_te;

/**
 * @brief: QSPI Interrupt Type Enumeration
 */
typedef enum qspi_interrupt_type_te{
    QSPI_Interrupt_TXE  = 0U, /*!< QSPI Transmit FIFO Empty Interrupt */
    QSPI_Interrupt_TXO  = 1U, /*!< QSPI Transmit FIFO Overflow Interrupt */
    QSPI_Interrupt_RXU  = 2U, /*!< QSPI Receive FIFO Underflow Interrupt */
    QSPI_Interrupt_RXO  = 3U, /*!< QSPI Receive FIFO Overflow Interrupt*/
    QSPI_Interrupt_RXF  = 4U, /*!< QSPI Receive FIFO Full Interrupt */
    QSPI_Interrupt_XRXO = 6U, /*!< QSPI XIP Receive FIFO Overflow Interrupt */
} qspi_interrupt_type_te;

/**
 * @brief: QSPI DMA Type Enumeration
 */
typedef enum qspi_dma_type_te{
    QSPI_DMA_RX = 0U, /*!< QSPI Receive DMA */
    QSPI_DMA_TX = 1U, /*!< QSPI Transmit DMA */
} qspi_dma_type_te;

/**
 * @brief: QSPI DMA Data Level Enumeration
 */
typedef enum qspi_dma_data_level_te{
    QSPI_DMA_Data_Level_0 = 0U, /*!< QSPI DMA Data Level 0 */
    QSPI_DMA_Data_Level_1 = 1U, /*!< QSPI DMA Data Level 1 */
    QSPI_DMA_Data_Level_2 = 2U, /*!< QSPI DMA Data Level 2 */
    QSPI_DMA_Data_Level_3 = 3U, /*!< QSPI DMA Data Level 3 */
    QSPI_DMA_Data_Level_4 = 4U, /*!< QSPI DMA Data Level 4 */
    QSPI_DMA_Data_Level_5 = 5U, /*!< QSPI DMA Data Level 5 */
    QSPI_DMA_Data_Level_6 = 6U, /*!< QSPI DMA Data Level 6 */
    QSPI_DMA_Data_Level_7 = 7U, /*!< QSPI DMA Data Level 7 */
} qspi_dma_data_level_te;

/**
 * @brief: QSPI address and instruction transfer format Enumeration
 */
typedef enum qspi_transfer_type_te{
    QSPI_Transfer_Type_TT0 = 0U, /*!< Instruction and Address will be sent in Standard SPI Mode. */
    QSPI_Transfer_Type_TT1 = 1U, /*!< Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by SPICTRLR0.SPI_FRF. */
    QSPI_Transfer_Type_TT2 = 2U, /*!< Both Instruction and Address will be sent in the mode specified by SPI_FRF. */
} qspi_transfer_type_te;

/**
 * @brief: QSPI Address Length Enumeration
 */
typedef enum qspi_address_length_te{
    QSPI_Address_Length_0Bits  = 0U,  /*!< No Address */
    QSPI_Address_Length_4Bits  = 1U,  /*!< 4-bits Address length */
    QSPI_Address_Length_8Bits  = 2U,  /*!< 8-bits Address length */
    QSPI_Address_Length_12Bits = 3U,  /*!< 12-bits Address length */
    QSPI_Address_Length_16Bits = 4U,  /*!< 16-bits Address length */
    QSPI_Address_Length_20Bits = 5U,  /*!< 20-bits Address length */
    QSPI_Address_Length_24Bits = 6U,  /*!< 24-bits Address length */
    QSPI_Address_Length_28Bits = 7U,  /*!< 28-bits Address length */
    QSPI_Address_Length_32Bits = 8U,  /*!< 32-bits Address length */
    QSPI_Address_Length_36Bits = 9U,  /*!< 36-bits Address length */
    QSPI_Address_Length_40Bits = 10U, /*!< 40-bits Address length */
    QSPI_Address_Length_44Bits = 11U, /*!< 44-bits Address length */
    QSPI_Address_Length_48Bits = 12U, /*!< 48-bits Address length */
    QSPI_Address_Length_52Bits = 13U, /*!< 52-bits Address length */
    QSPI_Address_Length_56Bits = 14U, /*!< 56-bits Address length */
    QSPI_Address_Length_60Bits = 15U, /*!< 60-bits Address length */
} qspi_address_length_te;

/**
 * @brief QSPI Instruction Length Enumeration
 */
typedef enum qspi_instruction_length_te{
    QSPI_Instruction_Length_0Bits  = 0U, /*!< No Instruction */
    QSPI_Instruction_Length_4Bits  = 1U, /*!< 4-bits Instruction length */
    QSPI_Instruction_Length_8Bits  = 2U, /*!< 8-bits Instruction length */
    QSPI_Instruction_Length_16Bits = 3U, /*!< 16-bits Instruction length */
} qspi_instruction_length_te;

/**
 * @brief QSPI Wait Cycles Enumeration
 */
typedef enum qspi_wait_cycles_te{
    QSPI_Wait_Cycles_0  = 0U,  /*!< No Wait Cycles */
    QSPI_Wait_Cycles_1  = 1U,  /*!< 1 Wait Cycles */
    QSPI_Wait_Cycles_2  = 2U,  /*!< 2 Wait Cycles */
    QSPI_Wait_Cycles_3  = 3U,  /*!< 3 Wait Cycles */
    QSPI_Wait_Cycles_4  = 4U,  /*!< 4 Wait Cycles */
    QSPI_Wait_Cycles_5  = 5U,  /*!< 5 Wait Cycles */
    QSPI_Wait_Cycles_6  = 6U,  /*!< 6 Wait Cycles */
    QSPI_Wait_Cycles_7  = 7U,  /*!< 7 Wait Cycles */
    QSPI_Wait_Cycles_8  = 8U,  /*!< 8 Wait Cycles */
    QSPI_Wait_Cycles_9  = 9U,  /*!< 9 Wait Cycles */
    QSPI_Wait_Cycles_10 = 10U, /*!< 10 Wait Cycles */
    QSPI_Wait_Cycles_11 = 11U, /*!< 11 Wait Cycles */
    QSPI_Wait_Cycles_12 = 12U, /*!< 12 Wait Cycles */
    QSPI_Wait_Cycles_13 = 13U, /*!< 13 Wait Cycles */
    QSPI_Wait_Cycles_14 = 14U, /*!< 14 Wait Cycles */
    QSPI_Wait_Cycles_15 = 15U, /*!< 15 Wait Cycles */
    QSPI_Wait_Cycles_16 = 16U, /*!< 16 Wait Cycles */
    QSPI_Wait_Cycles_17 = 17U, /*!< 17 Wait Cycles */
    QSPI_Wait_Cycles_18 = 18U, /*!< 18 Wait Cycles */
    QSPI_Wait_Cycles_19 = 19U, /*!< 19 Wait Cycles */
    QSPI_Wait_Cycles_20 = 20U, /*!< 20 Wait Cycles */
    QSPI_Wait_Cycles_21 = 21U, /*!< 21 Wait Cycles */
    QSPI_Wait_Cycles_22 = 22U, /*!< 22 Wait Cycles */
    QSPI_Wait_Cycles_23 = 23U, /*!< 23 Wait Cycles */
    QSPI_Wait_Cycles_24 = 24U, /*!< 24 Wait Cycles */
    QSPI_Wait_Cycles_25 = 25U, /*!< 25 Wait Cycles */
    QSPI_Wait_Cycles_26 = 26U, /*!< 26 Wait Cycles */
    QSPI_Wait_Cycles_27 = 27U, /*!< 27 Wait Cycles */
    QSPI_Wait_Cycles_28 = 28U, /*!< 28 Wait Cycles */
    QSPI_Wait_Cycles_29 = 29U, /*!< 29 Wait Cycles */
    QSPI_Wait_Cycles_30 = 30U, /*!< 30 Wait Cycles */
    QSPI_Wait_Cycles_31 = 31U, /*!< 31 Wait Cycles */
} qspi_wait_cycles_te;

/**
 * @brief QSPI Receive Data Sampling Edge Enumeration
 * 
 */
typedef enum qspi_rx_sampling_edge_te{
    QSPI_Rx_Sampling_Edge_Postive_Edge  = 0U, /*!< postive edge of clk will be used to sample the incoming data */
    QSPI_Rx_Sampling_Edge_Negative_Edge = 1U  /*!< negative edge of clk will be used to sample the incoming data */
} qspi_rx_sampling_edge_te;


/*!!!!!!!!!!!!!!!!!!< XIP Part >!!!!!!!!!!!!!!!!!!*/

/**
 * @brief: QSPI XIP Frame Format Enumeration
 */
typedef enum xip_frame_format_te{
    XIP_Frame_Format_Dual_SPI  = 1U, /*!< Dual SPI Format */
    XIP_Frame_Format_Quad_SPI  = 2U, /*!< Quad SPI Format */
    XIP_Frame_Format_Octal_SPI = 3U, /*!< Octal SPI Format */
} xip_frame_format_te;

/**
 * @brief: QSPI XIP Address And Instruction Transfer Format Enumeration
 */
typedef enum xip_transfer_type_te{
    XIP_Transfer_Type_TT0 = 0U, /*!< Instruction and Address will be sent in Standard SPI Mode. */
    XIP_Transfer_Type_TT1 = 1U, /*!< Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by XIP_CR.FRF */
    XIP_Transfer_Type_TT2 = 2U, /*!< Both Instruction and Address will be sent in the mode specified by XIP_CR.FRF */
} xip_transfer_type_te;

/**
 * @brief: QSPI XIP Address Length Enumeration
 */
typedef enum xip_address_length_te{
    XIP_Address_Length_0Bits  = 0U,  /*!< No Address */
    XIP_Address_Length_4Bits  = 1U,  /*!< 4-bits Address length */
    XIP_Address_Length_8Bits  = 2U,  /*!< 8-bits Address length */
    XIP_Address_Length_12Bits = 3U,  /*!< 12-bits Address length */
    XIP_Address_Length_16Bits = 4U,  /*!< 16-bits Address length */
    XIP_Address_Length_20Bits = 5U,  /*!< 20-bits Address length */
    XIP_Address_Length_24Bits = 6U,  /*!< 24-bits Address length */
    XIP_Address_Length_28Bits = 7U,  /*!< 28-bits Address length */
    XIP_Address_Length_32Bits = 8U,  /*!< 32-bits Address length */
    XIP_Address_Length_36Bits = 9U,  /*!< 36-bits Address length */
    XIP_Address_Length_40Bits = 10U, /*!< 40-bits Address length */
    XIP_Address_Length_44Bits = 11U, /*!< 44-bits Address length */
    XIP_Address_Length_48Bits = 12U, /*!< 48-bits Address length */
    XIP_Address_Length_52Bits = 13U, /*!< 52-bits Address length */
    XIP_Address_Length_56Bits = 14U, /*!< 56-bits Address length */
    XIP_Address_Length_60Bits = 15U, /*!< 60-bits Address length */
} xip_address_length_te;

/**
 * @brief: QSPI XIP Instruction Length Enumeration
 */
typedef enum xip_instruction_length_te{
    XIP_Instruction_Length_0Bits  = 0U, /*!< No Instruction */
    XIP_Instruction_Length_4Bits  = 1U, /*!< 4-bits Instruction length */
    XIP_Instruction_Length_8Bits  = 2U, /*!< 8-bits Instruction length */
    XIP_Instruction_Length_16Bits = 3U, /*!< 16-bits Instruction length */
} xip_instruction_length_te;

/**
 * @brief: QSPI XIP Wait Cycles Enumeration
 */
typedef enum xip_wait_cycles_te{
    XIP_Wait_Cycles_0  = 0U,  /*!< No Wait Cycles */
    XIP_Wait_Cycles_1  = 1U,  /*!< 1 Wait Cycles */
    XIP_Wait_Cycles_2  = 2U,  /*!< 2 Wait Cycles */
    XIP_Wait_Cycles_3  = 3U,  /*!< 3 Wait Cycles */
    XIP_Wait_Cycles_4  = 4U,  /*!< 4 Wait Cycles */
    XIP_Wait_Cycles_5  = 5U,  /*!< 5 Wait Cycles */
    XIP_Wait_Cycles_6  = 6U,  /*!< 6 Wait Cycles */
    XIP_Wait_Cycles_7  = 7U,  /*!< 7 Wait Cycles */
    XIP_Wait_Cycles_8  = 8U,  /*!< 8 Wait Cycles */
    XIP_Wait_Cycles_9  = 9U,  /*!< 9 Wait Cycles */
    XIP_Wait_Cycles_10 = 10U, /*!< 10 Wait Cycles */
    XIP_Wait_Cycles_11 = 11U, /*!< 11 Wait Cycles */
    XIP_Wait_Cycles_12 = 12U, /*!< 12 Wait Cycles */
    XIP_Wait_Cycles_13 = 13U, /*!< 13 Wait Cycles */
    XIP_Wait_Cycles_14 = 14U, /*!< 14 Wait Cycles */
    XIP_Wait_Cycles_15 = 15U, /*!< 15 Wait Cycles */
    XIP_Wait_Cycles_16 = 16U, /*!< 16 Wait Cycles */
    XIP_Wait_Cycles_17 = 17U, /*!< 17 Wait Cycles */
    XIP_Wait_Cycles_18 = 18U, /*!< 18 Wait Cycles */
    XIP_Wait_Cycles_19 = 19U, /*!< 19 Wait Cycles */
    XIP_Wait_Cycles_20 = 20U, /*!< 20 Wait Cycles */
    XIP_Wait_Cycles_21 = 21U, /*!< 21 Wait Cycles */
    XIP_Wait_Cycles_22 = 22U, /*!< 22 Wait Cycles */
    XIP_Wait_Cycles_23 = 23U, /*!< 23 Wait Cycles */
    XIP_Wait_Cycles_24 = 24U, /*!< 24 Wait Cycles */
    XIP_Wait_Cycles_25 = 25U, /*!< 25 Wait Cycles */
    XIP_Wait_Cycles_26 = 26U, /*!< 26 Wait Cycles */
    XIP_Wait_Cycles_27 = 27U, /*!< 27 Wait Cycles */
    XIP_Wait_Cycles_28 = 28U, /*!< 28 Wait Cycles */
    XIP_Wait_Cycles_29 = 29U, /*!< 29 Wait Cycles */
    XIP_Wait_Cycles_30 = 30U, /*!< 30 Wait Cycles */
    XIP_Wait_Cycles_31 = 31U, /*!< 31 Wait Cycles */
} xip_wait_cycles_te;

/**
 * @brief: QSPI XIP Instruction Phase Enumeration
 */
typedef enum xip_instruction_phase_te{
    XIP_No_Instruction = 0U, /*!< XIP transfers will not have instruction phase */
    XIP_Instruction    = 1U  /*!< XIP transfers will have instruction phase */
} xip_instruction_phase_te;

/**
 * @brief: QSPI XIP Mode Bits Length Enumeration
 */
typedef enum xip_mode_bits_length_te{
    XIP_ModeBits_2  = 0U, /*!< Mode bits length equal to 2 */
    XIP_ModeBits_4  = 1U, /*!< Mode bits length equal to 4 */
    XIP_ModeBits_8  = 2U, /*!< Mode bits length equal to 8 */
    XIP_ModeBits_16 = 3U, /*!< Mode bits length equal to 16 */
} xip_mode_bits_length_te;

/**
 * @brief: QSPI Configuration Structure Definition
 */

typedef struct qspi_config_ts {
    /* CTRLR0 */
    qspi_data_frame_size_te data_frame_size;       /*!< QSPI Data Frame Size */
    qspi_data_frame_format_te frame_format;        /*!< QSPI Data Frame Format */
    qspi_serial_clock_phase_te scph;               /*!< QSPI Serial Clock Phase */
    qspi_serial_clock_polarity_te scpol;           /*!< QSPI Serial Clock Polarity */
    qspi_transfer_mode_te transfer_mode;           /*!< QSPI Transfer Mode */
    qspi_control_frame_size_te control_frame_size; /*!< QSPI Control Frame Size */
    qspi_frame_format_te spi_frame_format;         /*!< QSPI Frame Format */

    /* CTRLR1 */
    uint16_t data_frames_number; /*!< QSPI Transfer Number(in units of QSPI Data Frame Size) */
    /* BAUDR */
    uint16_t sckdv; /*!< QSPI Baud Rate*/

    /* TXFTLR */
    uint8_t transfer_start_fifo_number; /*!< QSPI Transfer start FIFO level */
    uint8_t transmit_fifo_threshold;    /*!< QSPI Transmit FIFO Threshold  */

    /* RXFTLR */
    uint8_t receive_fifo_threshold; /*!< QSPI Receive FIFO Threshold */

    /* RXSDR */
    qspi_rx_sampling_edge_te sampling_edge; /* QSPI Receive Data Sampling Edge */
    uint8_t sampling_delay;                 /* QSPI Receive Data Sample Delay */

    /* SPICTRLR0 */
    qspi_transfer_type_te trans_type;          /* QSPI Address and instruction transfer format */
    qspi_address_length_te addr_l;             /* QSPI Address Length */
    qspi_instruction_length_te inst_l;         /* QSPI Dual/Quad/Octal mode instruction length in bits */
    qspi_wait_cycles_te dummy_cycles;          /* QSPI Wait Cycles */
    FunctionState clock_stretching_capability; /* clock stretching capability */

} qspi_config_ts;

/**
 * @brief: XIP Configuration Structure Definition
 */
typedef struct xip_config_ts
{
    xip_frame_format_te frame_format; /*!< XIP Frame Format */

    xip_instruction_phase_te inst_en; /*!< XIP Instruction Phase Enable */
    xip_instruction_length_te inst_l; /*!< XIP Instruction Length */
    uint16_t inst_value;              /*!< XIP Instruction  */

    xip_address_length_te addr_l;    /*!< XIP Address Length */
    xip_wait_cycles_te dummy_cycles; /*!< XIP Wait Cycles */
    xip_transfer_type_te trans_type; /*!< XIP Address And Instruction Transfer Format */

    FunctionState mode_bits_en;          /*!< Mode Bits Enable In XIP */
    xip_mode_bits_length_te mode_bits_l; /*!< XIP Mode Bits Length */
    uint16_t mode_bits_value;            /*!< XIP Mode Bits Value */

    FunctionState continus_transfer_en; /*!< Continuous Transfer In XIP */
    FunctionState pre_fetch_en;         /*!< XIP Pre-Fetch Functionality */

    uint16_t wrap_inst_value;           /*!< XIP Wrap Instruction */
    uint8_t continus_transfer_time_out; /*!< XIP Continus Transfer Time Out */
} xip_config_ts;

/*!<---------------End of Definitions--------------->!*/

/*******************************************************************************
 * APIs
 ******************************************************************************/

/* QSPI Initialization Function */
void QSPI_GetDefault(qspi_config_ts *qspi_config);
void QSPI_Init(qspi *qspix, qspi_config_ts *qspi_config);

/* QSPI Operation Function */
void QSPI_Cmd(qspi *qspix, FunctionState state);
void QSPI_Change_CTRLR0(qspi *qspix, qspi_data_frame_size_te data_size, qspi_frame_format_te spi_frame_format, qspi_transfer_mode_te transfer_mode);
void QSPI_Change_CTRLR1(qspi *qspix, uint16_t fifo_num);

void QSPI_Clock_Divider(qspi *qspix, uint16_t div);
void QSPI_Change_Transfer_Start_FIFO_Level(qspi *qspix, uint8_t value);
void QSPI_Change_SPI_Control_Register(qspi *qspix, qspi_transfer_type_te type, qspi_address_length_te addr_l, qspi_wait_cycles_te dummy_cycle);

/* QSPI Status Related Function*/
FlagStatus QSPI_Get_Status(qspi *qspix, qspi_status_type_te status);

/* QSPI DMA Related Function */
void QSPI_DMA_Level(qspi *qspix, qspi_dma_type_te dma_type, uint8_t level);
void QSPI_DMA_Cmd(qspi *qspix, qspi_dma_type_te dma_type, FunctionState state);

/* XIP Initialization Functions */
void XIP_GetDefault(xip_config_ts *xip_config);
void XIP_Init(qspi *qspix, xip_config_ts *xip_config);

/* QSPI Standard Full Duplex Related Function */
void QSPI_STD_Init(qspi *qspix, uint16_t sck_dv);
uint8_t QSPI_STD_WriteRead(qspi *qspix, uint32_t data);

/*!<---------------End of APIs--------------->!*/
#endif
/*!<---------------End of _LT168_QSPI_H --------------->!*/
